Integrated circuit (IC) devices generally include an interlayer dielectric (ILD) formed over the wafer substrate. The ILD is subsequently patterned to form metal-filled recessed features, such as contacts and interconnects. For example, conductive metals with low resistivity and high electromigration resistance form the features and define the performance of the contact and interconnect structures. Some conductive metals may undesirably diffuse into the dielectric material surrounding the recessed features and negatively impact the dielectric properties. Therefore, a diffusion barrier layer is typically deposited between the dielectric and conductive metal to prevent migration of conductive metals. However, barrier faults may be introduced during the deposition process of the barrier layer, resulting in premature failure of the IC.
From the foregoing discussion, it is desirable to provide improved methods for forming the barrier layers and maintaining barrier integrity.